Senior-level FPGA Electronic R&D Engineer

Jaguar Industri Ltd

We’re looking for a Senior-level FPGA Electronic R&D Engineer to tackle the toughest aspects of computer hardware: from 8–12-layer, controlled-impedance PCBAs to advanced FPGA IP subsystems. You’ll own every step of a complex, high-speed board’s lifecycle, driving signal-integrity, power-integrity, EMI mitigation, and manufacturability at top performance margins. If you thrive on solving the hardest layout puzzles you are a good fit.

Responsibilities
• Stack-up & Material Selection
o Define 8–12-layer PCB stack-ups for optimal impedance control, power/ground coupling, and thermal management
o Select advanced laminates, based on insertion loss, Dk/Df, and cost trade-offs
• High-Speed Routing & SI/PI Analysis
o Route differential pairs (PCIe Gen4/5, DDR4/5, USB4, MIPI-CSI, HDMI) with strict length-matching, crosstalk minimization, and via-stitching strategies
o Perform pre- and post-layout signal-integrity and power-integrity simulations using tools like HyperLynx or similar.
o Lead EMI/EMC mitigation: split planes, guard rings, common-mode choke placement, and chassis bonding
• Full-Chain Execution
o Drive end-to-end PCB design: schematic capture, part library vetting, detailed layout, DFM review, and fab/vendor qualification
o Author and enforce design rules (clearances, impedance, via back-drilling) to meet yield and reliability targets
• DFX & Test
o Develop boundary-scan (JTAG) test strategies, bed-of-nails/pogo-pin fixtures, and in-circuit test programs
o Troubleshoot prototypes using high-bandwidth oscilloscopes, VNAs and other equipment.


FPGA IP & System Integration
• Custom & Vendor IP
o Architect and verify custom RTL for high-speed transceivers, DDR controllers, and camera-interface logic
o Integrate and validate vendor IP cores (e.g. PCIe Gen4/5, MIPI, Ethernet) under tight timing budgets
• Hardware Bring-Up & Debug
o Collaborate with mechanical and software teams to script automated bring-up routines
o Perform lab-level debug: protocol-analyzer captures, eye-diagram measurements, and bit-error-rate testing

Qualifications

Qualifications
• Education & Experience
o M.S. or Ph.D. in Electrical Engineering (or equivalent) with = 7 years focused on multilayer, high-speed PCB design
o Proven track record delivering 8–12-layer boards with PCIe Gen4/5, DDR4/5, USB4, MIPI, HDMI or equivalent interfaces
• Technical Expertise
o Deep knowledge of controlled-impedance routing, differential-pair tuning, crosstalk suppression, and via back-drilling
o Mastery of SI/PI simulation tools (HyperLynx, Keysight) and EMI/EMC mitigation techniques
o Strong grasp of DFX (DFM, DFT, DFA) methods, boundary-scan, and advanced in-circuit test design
• Tools & Processes
o Proficient in Altium Designer, Solid Works.
o Experience defining and enforcing enterprise-scale design rules and library management
o Skilled in reading/measuring with oscilloscopes (> 10 GHz BW), VNA

• Soft Skills
o Excellent communicator, able to articulate complex SI/PI issues across hardware, firmware, and manufacturing teams
o Willing to develop cutting edge hardware with a focus on quality